1. Field of the Invention
The invention relates to a method for manufacturing a semiconductor memory device.
2. Background Art
Conventional stacked memory technology forms normal planar memory cells on a silicon substrate, repeats the forming step for each layer, and therefore is not suited to large-capacity memory because many manufacturing steps are performed for each layer. Therefore, technology is proposed to realize large-capacity memory with high manufacturing efficiency by collectively making holes to pass from the uppermost layer to the lowermost layer of a stacked structure including alternately stacked word line electrode layers and inter-layer dielectric layers and filling columnar silicon into the holes as channels (for example, JP-A 2008-171918 (Kokai)). Such technology has a structure in which the columnar silicon covers the word line electrode layers at a constant spacing to form a memory cell transistor by providing a charge storage layer for retaining data at the intersection between each word line electrode layer and the silicon column.
JP-A 2008-171918 (Kokai) discloses technology performing metal siliciding of electrode layers adjacent to a trench to realize reduced resistance by making the trench adjacent to a silicon column, exposing the electrode layers (silicon layers) inside the trench, forming a metal film on the side wall of the trench, and subsequently performing annealing.
In such a case, there is a risk that shorts may occur between the electrode layers when the metal silicide comes into contact between the electrode layers above and below due to volume expansion of the metal silicide during annealing.